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CXB1454R
VGA/SVGA/XGA 24bit Receiver
Description CXB1454R is the 1 chip deserializer for VGA/SVGA/ XGA 24bit color digital RGB, and meet to the Gigabit Video Interface specification. Features * 1 chip receiver for serial transmission of 24-bit color VGA/SVGA/XGA picture * On chip cable equalizer circuit to compensate the cable loss * On chip PLL circuit for data and clock recovery * On chip panel mode automatically selectable circuit * TTL compatible I/O * Support 1 pixel/shiftclock mode with 1 chip and 2 pixel/shiftclock mode with 2 chips * +3.3V single power supply * Low power consumption * 64pin plastic LQFP package with body size 14mm x 14mm Structure Bipolar silicon monolithic IC
LPFB LPFA VEES VEEA VccA
64 pin LQFP (Plastic)
Absolute Maximum Ratings * Supply voltage Vcc * Storage temperature Tstg * Allowable power dissipation PD
4.0 -65 to +150 1710
V C mW
Recommended Operating Condition * Supply voltage Vcc 3.3 0.16 * Operating temperature Topr 0 to +60
V C
TESTEXN
REFRQN
REFRQP
SDATAN
SDATAP
TESTDT
TESTSB
PANEL1
PANEL0
Block Digagram & Pin out
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
LOS
REXT
CNTL 49 DE 50 SFTCLK 51 VEET 52 VccT 53 VEEG 54 VccG 55 HSYNC 56 VSYNC 57 B7 58 B6 59 VEEG 60 VccG 61 B5 62 B4 63 VccT 64 Decoder Serial to Parallel Converter CDR PLL Cable EQ
32 CLKPOL 31 R0 30 R1 29 VEET 28 VccT 27 VEEG 26 VccG 25 R2 24 R3 23 R4 22 R5 21 VEEG 20 VCCG 19 R6
18 R7 17 VEET
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
VEET
VccT
VEET
Fig. 1. Block Diagram & Pin out
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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VccT
B2
G6
G7
G5
G4
G3
G2
G1
G0
B3
B1
B0
E98X24B03
CXB1454R
Pin List Tab. 1. Power/Ground Pin Name VCCT VEET VCCG VEEG VCCA VEEA VEES Pin Number 8, 16, 28, 53, 64 1, 9, 17, 29, 52 20, 26, 55, 61 21, 27, 54, 60 44 45 46 Descriptions TTL power surpply, should be connected to 3.3V 5% TTL ground, connected to 0V Logical core power surpply, connected to 3.3V 5% Logical core ground, connected to 0V Analog power surpply, connected to 3.3V 5% Analog ground, connected to 0V Analog substrate, connected to 0V
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CXB1454R
Tab. 2. Digital Signals Pin Name SFTCLK Pin Number 51 Type TTL out Descriptions Shift clock, for the data fetch at falling or rising edge
VCCT
Equivalent circuit
RED (7 to 0) 18, 19, 22, 23, 24, 25, 30, 31, GRN (7 to 0) 6, 7, 10, 11, TTL out 12, 13, 14, 15, BLU (7 to 0) 58, 59, 62, 63, 2, 3, 4, 5 HSYNC VSYNC CNTL DE LOS 56 57 49 50 36 TTL out TTL out TTL out TTL out TTL out TTL in TTL in
Pixel data
TTL-OUT
Hsync data Vsync data Control data Display enable data Los of signal Panel mode select switch Trigger edge select switch
VCCT 6k 6k VCCG
VEET
PANEL (1, 0) 35, 34 CLKPOL 32
TESTEXN TESTDT TESTSB
43, 37, 38
TTL-IN
TTL in
Reserved for TEST under fabrication
VEET
300
VEEG
VCCG
SDATAP/N
40, 41
Rx
Serial input
SDATAP/N REFRQP/N
REFRQP/N
39, 42
Rx
Refclk request
VEEG
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CXB1454R
Tab. 3. Special Pin Name Pin Number Descriptions
VCCG
Equivalent circuit
REXT
33
External Resister
REXT VEEG
VCCA
LPFA LPFB
LPFA/B
47, 48
External loop filter
VEEA
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CXB1454R
Electrical characteristics Tab. 4. Absolute Maximum Rating Description Power supply voltage TTL DC input voltage TTL output current (High) TTL output current (Low) Serial input pin voltage REFRQ output pin voltage Storage temperature Symbol VCC VI_T IOH_T IOL_T Vsdin VRQout Tstg Min. -0.3 -0.5 -20 0 -0.5 0.5 -65 Typ. Max. 4 5.5 0 20 VCC + 0.5 VCC + 0.5 150 Unit V V mA ' mA V V C Comments
Tab. 5. Recommended Operating Conditions Description Power supply voltage (Include VCCT5) Operating temperature Symbol VCC Topr Min. 3.135 0 Typ. 3.3 Max. 3.465 60 Unit V C Comments
Tab. 6. DC Characteristics (Under the recommended conditons. See Tab. 5) Description Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Output HIGH voltage (TTL) Output LOW voltage (TTL) Output HIGH current (REFRQ) Output LOW current (REFRQ) Input dynamic range (SDATA) Input dynamic range (SDATA) Symbol VIH_T VIL_T IIH_T IIL_T VOH_T VOL_T IOH_RQ IOL_RQ VIM_SD VID_SD -0.1 7.8 VCC - 0.4 -0.5 325 Supply current ICC 350 465 mA 0 -400 2.25 0.5 +0.1 11 VCC + 0.2 +0.5 440 Min. 2 0 Typ. Max. 5.5 0.8 20 Unit V V A A V V mA mA V V mA VIN = VCC VIN = 0 IOH = -0.2mA IOL = 4mA See Fig. 3, 4 REXT = 1.3k Common mode voltage Differential voltage 65MHz, All low pattern, Outputs open 65MHz, Worst case pattern See Fig. 8 Outputs open Conditions
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CXB1454R
VCCA/G/T CXB1454R 37 TESTDT REFRQP 39 VCC 38 TESTSB 43 TESTEXN REFRQN 42
50 A 150 A
50
150
VEEA/G/T
Fig. 2. IOH_RQ and IOL_RQ DC measurement
TESTDT
TESTSB
TESTEXN
Fig. 3. IOH_RQ and IOL_RQ DC measurement setting Electrical characteristics Tab. 7. AC Characteristics (Under the recommended conditons. See Tab. 5) Description Minimum SFTCLK frequency Maximum SFTCLK frequency SFTCLK duty factor Pixel/Sync/Cntl/DE setup to SFTCLK Symbol Fsftclk Dsftclk Min. 65.0 40 16 10 5 17 11 6 3 2.5 4.5 2 0.9 50 0.5 0.1 -6- 60 Typ. Max. 25.0 Unit MHz MHz % ns ns ns ns ns ns ns ns ns ns s s s s Vth = 1.4V, CL = 10pF Vth = 1.4V, CL = 10pF 25MHz 40MHz 65MHz Vth = 1.4V, CL = 10pF 25MHz 40MHz 65MHz 0.8 to 2.0V, CL = 10pF 2.0 to 0.8V, CL = 10pF 0.8 to 2.0V, CL = 10pF 2.0 to 0.8V, CL = 10pF Conditions
Tsetup
Pixel/Sync/Cntl/DE hold to SFTCLK SFTCLK rise time SFTCLK fall time Pixel/Sync/Cntl/DE rise time Pixel/Sync/Cntl/DE fall time CLOCK mode assert time CLOCK mode deassert time LOS signal assert time LOS signal deassert time
Thold
Torc Tofc Tofd Tord TAclk TDclk TAlos TDlos
CXB1454R
VCCA/G/T TTLout Cprobe VCC CXB1454R CL' VEEA/G/T CL' + Cprobe = 10pF oscilloscope
Fig. 4. Pixel/Sync/Cntl/DE waveform measurement
Timing Chart
1/Fsftclk
2.0V SFTCLK 0.8V Torc Setup/hold time is refered from rising edge in CLKPOL = GND falling edge in CLKPOL = Vcc or OPEN Tofc Dsftclk/Fsftclk Vth
Tsetup Thold Tord 2.0V 0.8V Tofd
REDxx GRNxx BLUxx H/Vsync CNTL DE
Fig. 5. TTL output timing
Pixel Sync/Cntl/DE SftClk
error
Indeterminate TAclk
REFRQP REFRQN
Indeterminate TDclk
SDATAP SDATAN
Fig. 6. Refclk request timing -7-
CXB1454R
SDATAP SDATAN TDlos
NRZ data TAlos
LOS
Fig. 7. Idle mode timing
T
T
SFTCLK
f
RGB <7, 5, 3, 1>
f/2
RGB <6, 4, 2, 0>
f/2
Fig. 8. Worst case test pattern
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CXB1454R
CLKPOL Pin Control The CLKPOL pin is used to select the SFTCLK trigger edge. (See Table 8.) The CLKPOL pin is open High TTL input. Table 8. SFTCLK Polarity CLKPOL L H Receiver operation trigger Rising edge Falling edge
PANEL1 and 0 Pin Control The PANEL1 and 0 pins are used to select the panel mode. (See Table 9.) For the normal use, the all frequencies of SFTCLK (25MHz to 65MHz) can be covered by fixing both PANEL1 and 0 to High. The PANEL1 and 0 pins are open High TTL inputs. Table 9. Panel Mode PANEL1 L L H H PANEL0 L H L H Supporting panel size VGA (640 x 480) SVGA (800 x 600) XGA (1024 x 768) VGA to XGA Shift clock 25MHz 40MHz 65MHz 25MHz to 65MHz Serial rate 750Mbps 1200Mbps 1950Mbps 750Mbps to 1950Mbps
Test Pin Control The TESTEXN, TESTDT and TESTSB pins are for test only. Select normal mode. (See Table 10.) The TESTEXN, TESTDT and TESTSB pins are open High, TTL inputs. Table 10. Test Mode TESTEXN L H TESTDT X H TESTSB X H Operation mode Test mode Normal mode
LOS Pin Output The LOS pin shows the absence of proper level of SDATA signal. The LOS pin is High when the connector is disconnected or the transmitter is idle. The LOS pin is TTL output.
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CXB1454R
Applications CXB1454R GVIF receiver is applied to the digital RGB signal transmission for P/C with LCD monitor Video on demand system Monitoring system Graphical controller Projector Digital TV monitor Car navigation system with GVIF transmitter, CXB1455R.
CXB1455R GVIF Transmitter
RED (7 to 0) GRN (7 to 0) BLU (7 to 0) SYNC/CNTL/DE SHIFTCLOCK
8
Encoder
8 8 4
Parallel to Serial Converter
Cable Driver
PLL
STP or Twin axial
8
RED (7 to 0) GRN (7 to 0) BLU (7 to 0) SYNC/CNTL/DE SHIFTCLOCK
Cable Equalizer
Decoder
Serial to Parallel Converter
8 8 4
PLL CXB1454R GVIF Receiver
Fig. 9. Block Diagram of GVIF transceiver chip set
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CXB1454R
Application Cicuit
VCC 0.1 to 0.4n (3) E 0.1 to 0.4n (3) 33 16V 0.1 to 0.4n (3) Connector Differential cable
(1) CHIP RESISTOR (1%) (2) CHIP CAPACITOR (3) FORMED BY THE PRINTED CIRCUIT PATTERN (L = 0.5 to 1.0mm / W = 0.5 to 1.0mm)
470 (1) 0.1 100p (2)
150 (1)
100 (1)
150 (1) 1.3k (1) 330 Vcc SW1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
330
470 (1)
(2)
47p 47p (2) (2)
VEES
SDATAP
SDATAN
REFRQN
TESTEXN
REFRQP
TESTSB
TESTDT
PANEL1
PANEL0
LPFB
LPFA
VEEA
VccA
LOS
REXT
330
H: FALLING EDGE TRIGGER L: RISING EDGE TRIGGER
49 CNTL 50 DE 51 SFTCLK 0.1 (2) 52 VEET Vcc 53 VccT 54 VEEG E 55 VccG 56 HSYNC 57 VSYNC 58 B7 59 B6 0.1 (2) 60 VEEG E 61 VccG 62 B5 63 B4 Vcc 64 VccT
CLKPOL 32 R0 31 R1 30 VEET 29 VccT 28 VEEG 27 VccG 26 R2 25 R3 24 R4 23 R5 22 VEEG 21 VCCG 20 R6 19 R7 18 VEET 17 E 0.1 (2) E 0.1 (2)
VEET
VccT
VEET
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
0.1 (2) Vcc Vcc 0.1 (2)
VccT
G6
G7
G5
B1
G4
B0
G3
G2
G1
B3
G0
B2
0.1 (2)
CNTL
VSYNC
DE
SFTCLK
HSYNC
7 MSB
6
5
4
3
2
1
0 LSB
7 MSB
6
5
4
3
2
1
0 LSB
76 MSB
5
Vcc
4 3
2
1
0 LSB
BLUE DATA
GREEN DATA
RED DATA
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Fig. 10. Recommended application circuit
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CXB1454R
Recommended Printed Circuit Board Structure
L1: I1: L2: I2: L3: I3: L4: Cu plate (18m) + solder coat Fiber-glass epoxy core (0.3mm) Cu plate (36m) Fiber-glass epoxy core (0.8mm) Cu plate (36m) Fiber-glass epoxy core (0.3mm) Cu plate (18m) + solder coat
Fig. 11. Recommended Printed Circuit Board Structure Recommended Printed Circuit Board Pattern POWER and special signal routing example
0.5mm
G Through hole to the GND plane (L2) E T Through hole to the VCCE/VCCG plane (L3) Through hole to the VCCT plane (L3) Chip capacitor FET Chip resistor L2 doesn't have plane in this area 6mm G
48
TESTEXN REFRQN SDATAP REFRQP SDATAN TESTSB TESTDT PANEL1 PANEL0
33
49
REXT
LPFB
LPFA
VEES
VEEA
VccA
LOS
CNTL DE SFTCLK VEET
CLKPOL R0 R1 VEET VccT
32
G
G
VccT VEEG VccG HSYNC VSYNC B7 B6 VEEG
G E
G E
VEEG VccG R2 R3 R4 R5
T T
T T
T T
T T
VEEG VccG R6 R7 VEET
G E
G
E
VccG B5 B4
64 T
VccT B0 VEET VEET VccT G2 G1 G0 B1 VccT G7 G6 G5 G4 G3 B3 B2
17 G
G
T
Fig. 12. Recommended Printed Circuit Board Pattern - 12 -
T
G
1
16
CXB1454R
Micro Strip Line For maximum performance, the impedance between the pins SDDATAP/N of the LSI and the footprint of the connector should be 50 using a micro strip line. 50 impedance can be reached when using 0.5mm width pattern lines on L1 using this circuit board structure. The length of the lines should be identical and throughhole should not be used. L2 is recommended as the large ground plane. Terminators Terminators (100 resistor) should be located as close to the LSI as possible. Filter Devices and Reference Registors Capacitors and resistors which are connected to LPFA/B and REXT are filters and reference resistors. The region of Layer 2 (L2) is under the device and conductive patterns. The ground plane should be taken off in order to reduce parasitic capacitors. Bypass Capacitors Bypass capacitors (0.1F SMD type) should be located as close to the pins as possible. Refer to the recommendation.
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CXB1454R
Recommendation for Cable and Connector Characteristics The GVIF system uses terminators at both ends (transmitter and receiver), a cable equalizer and a small amplitude differential signal. In order to solve the problems of high speed data transmission such as signal reflection, reduce the signal level and EMI. In order to achieve the best solution, note the following:
Tx termination 50 Rx termination 100 Tx LSI Rx LSI
Microstrip line (50)
Foot print
Connector
Cable (diff. 100)
Connector
Foot print
Microstrip line (50)
It is important to note the following issues for a good data transmission system: * Good impedance matching Differential impedance should be fit to the recommended template on the next page. * Cable loss should be small and the loss curve should be smooth. Maximum loss should be less than 15dB at 1GHz for the CXB1454R which has a built-in cable equalizer. See the next page. * Skew of POS/NEG (differential signal) should be small Less than 12% of 1-bit time or 160ps@VGA, 100ps@SVGA, 60ps@XGA. * Good EMI performance cable and connectors. In order to satisfy these issues, the recommendations are as follows: * Use the differential cable which provides good controlled impedance, low loss and good skew matching. A shielded twisted pair (STP) cable is recommended. * Use a low reflectance connector. * To minimize interference from other signals, high speed signal lengths should be identical. * Use double shielded cable.
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CXB1454R
Recommended Transmission Path : Differential impedance template
Zo () 150 110 106 94 90 75
< 500ps
< 500ps
Microstrip line
Foot print
Connector
Connector
Foot print
Microstrip line
Recommended Transmission Path : Attennation Characteristics
Loss
< 15dB 2dB Measured curve
Fitting curve Frequency 1GHz
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CXB1454R
TTL output waveform with CL = 10pF
SFTCLK 65MHz TTL output
B0 T 65Mb/s TTL output
1.00V/div
1.00V/div
5ns/div
ATTEN 40dB RL 119.2dBV
SFTCLK Power spectrum
10dB/
D
R
C
CENTER 65.000MHz RBW 100kHz VBW 100kHz
SPAN 9.900MHz SWP 50.0ms
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CXB1454R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
16.0 0.2 48 49 14.0 0.1 33 32 0.1 1.7MAX
B A 17 1 0.8 16 0.13 M
64
0.25 0.1 0.1 + 0.08 0.37 - 0.07
(0.5)
DETAIL B
EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.7g
+ 0.08 0.37 - 0.07
(15.0) (0.5)
0 to 10 DETAIL A NOTE: Dimension "" does not include mold protrusion.
0.6 0.2
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L02 LQFP064-P-1414 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
- 17 -
(0.125)
(0.35)
0.145 0.04
Sony Corporation

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